The present disclosure relates to level shifters mounted in semiconductor integrated circuits having different power supply voltages, and more particularly to level shifters suitable for semiconductor integrated circuits including transistors having different breakdown voltages and threshold voltages, and manufactured in a miniaturized process.
In recent years, analog circuits and digital circuits have been mixed in a single semiconductor integrated circuit. Moreover, semiconductor integrated circuits have equipped with more and more functions. In a semiconductor integrated circuit, while an interface including numbers of analog circuits has had a power supply voltage (I/O voltage) of about 2.5 V or 3.3 V, a power supply voltage (core voltage) of a digital circuit has decreased to about 1.1 V. That is, recent semiconductor integrated circuits have generally had different power supply voltages. This requires a level shifter for converting a signal of low voltage amplitude, which is output from a core operating at a low voltage, to a high voltage amplitude, and transmitting the signal to a circuit operating at a high voltage.
There is a conventional level shifter logically inverts an input pulse signal of low voltage amplitude using an inverter circuit operating at a low voltage, and shifts the level of complementary pulse signals of low voltage amplitude, which include an input signal and an output signal of the inverter circuit, using two level shifters performing opposite operation. This enables high-speed operation with low power consumption (see, for example, Japanese Patent Publication No. 2004-40262). Another conventional level shifter does not include any inverter circuit which performs low-voltage operation for logically inverting an input pulse signal of low voltage amplitude. A DC component of the input pulse signal of low voltage amplitude is eliminated, and the signal is biased by an inverter circuit, which perform high-voltage operation and includes an input and an output, which are short-circuited. Then, the signal is input to gates of a Pch transistor and an Nch transistor forming the inverter circuit operating at a high voltage. (See, for example, Japanese Patent Publication No. 2003-110419).
In a miniaturized manufacturing process of 45 nm process or later generation, a circuit, which includes transistors having a low breakdown voltage and a low threshold voltage ranging from about 0.3 to about 0.4 V out of transistors operating at a low voltage, is under the following layout constraint. Channel directions of the transistors, i.e., directions of drains, gates, and sources need to be the same in order to prevent degradation in the characteristics of the transistors. For example, in the level shifter of Japanese Patent Publication No. 2004-40262, the inverter circuit, which logically inverts the input pulse signal of low voltage amplitude, includes transistors having a low breakdown voltage and a low threshold voltage similar to the transistors used in a digital circuit. Thus, the inverter circuit is under the layout constraint in a miniaturized manufacturing process. Assume that the level shifter has a rectangular circuit pattern. Even if a semiconductor integrated circuit has a vacant region in which the circuit pattern can be positioned after being rotated by 90°, the positioning cannot be made and the vacant region of the semiconductor integrated circuit cannot be efficiently used.
On the other hand, even if the inverter circuit includes high threshold voltage transistors free from the layout constraint instead of the low threshold voltage transistors, the level shifter does not accurately operate. It is thus necessary to prepare another circuit pattern of the level shifter, in which the channel directions of the low threshold voltage transistors are rotated by 90° to utilize a vacant region of a semiconductor integrated circuit efficiently. This increases, however, the number of designing steps.
Low-threshold voltage transistors have problems such as relatively large leakage currents, and aging degradation in the characteristics caused by kickback from a high voltage power supply. In particular, the level shifter operates at high speed and with low power consumption by employing the creative configuration of the high voltage circuits, and thus the degradation in the characteristics of the low voltage circuits directly influences the high-speed operation of the level shifter.
In this respect, for example, the level shifter of Japanese Patent Publication No. 2003-110419 does not include any low threshold voltage transistor, and thus the problems such as the layout constraint, leakage currents, and aging degradation in the characteristics are less likely to occur. However, the level shifter requires a capacitive element to eliminate the DC component of the input pulse signal of the low voltage amplitude, thereby increasing the circuit scale. Also, since the input and output of the inverter circuit operating at a high voltage are short-circuited to generate a bias voltage, through currents always flow to the inverter circuit, thereby increasing the current consumption.
Therefore, there is a need for a level shifter, which is freely positioned in a miniaturized manufacturing process with a small circuit scale, low power consumption, and less aging degradation.